About bitwiz#

I’m Alexis, an FPGA engineer with 5+ years building high-performance digital systems.

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Background#

My work spans medical devices, big tech infrastructure, and custom silicon projects. I specialize in:

  • Streaming systems - High-throughput data pipelines and DMA engines
  • SerDes integration - Multi-gigabit serial links (PCIe, Ethernet, custom)
  • Verification automation - Cocotb frameworks, SVA, constrained random
  • Timing closure - Clock domain crossings, multicycle paths, physical optimization

Current Focus#

  • DDR4/DDR5 memory subsystems
  • 100G+ Ethernet implementations
  • Hardware/software co-verification
  • Open-source FPGA tooling

Philosophy#

Write RTL like someone else will have to debug it at 2am. Because that someone might be you.

I believe in:

  • Readable code over clever code
  • Assertions everywhere - if it can go wrong, check it
  • Automation - if you do it twice, script it
  • Documentation - but not too much

This Site#

bitwiz is where I share projects, techniques, and tools from my work. Everything here is meant to be practical and applicable to real designs.

Contact#

📧 Email: [email protected]

I read every email, though response times vary based on workload.