Articles

Reference notes on FPGA timing closure, constraints, and verification.

Topics include timing analysis, constraint methodology, and RTL design patterns.

Resets: The Timing Event You Forgot

2026-01-03

Understanding reset timing - recovery, removal, async assert sync deassert, reset trees, and why sporadic startup failures haunt your design

CDC: Two Flip-Flops Are Not Magic

2026-01-02

#FPGA #CDC #timing #metastability #hardware

Understanding clock domain crossing - synchronizers, metastability, pulse transfer, gray code, and why 2-flop sync only works for levels

Silicon Real Estate: Your Resource Budget

2025-12-31 [Updated: 2026-01-02]

#FPGA #utilization #timing #hardware

Understanding FPGA resource utilization - LUTs, registers, BRAM, DSPs, and why 94% utilization means your design won’t close timing

Pipelining Without Breaking Your Protocol

2025-12-30 [Updated: 2026-01-02]

#FPGA #pipelining #timing #protocols #hardware

Understanding how to add pipeline registers without breaking valid/ready handshakes - skid buffers, register slices, and protocol-correct timing fixes

Understanding Timing Analysis

2025-12-28

#FPGA #timing #STA #hardware

A deep dive into static timing analysis - understanding slack, path delays, clock skew, and why period minus data path is not your margin

Constraints: The Contract You Forgot to Sign

2025-12-23

#FPGA #timing #constraints #CDC #hardware

Understanding FPGA timing constraints - clocks, I/O delays, CDC, and why ‘Timing Met’ means nothing without proper constraints

Your FPGA Lives a Lifetime While You Blink

2025-12-22

#FPGA #timing #10GbE #hardware

Understanding FPGA timing at 156.25 MHz - where half a nanosecond means the difference between working and failing