bitwiz calc

Data Clock Frequency

What: Clock frequency of the source domain whose signal crosses to the destination.

Why: Appears in MTBF denominator. Higher frequency = more signal transitions = more opportunities for metastability per second.

Find it: The clock driving the register whose output enters the synchronizer chain.

Sampling Clock Frequency

What: Clock frequency of the destination domain capturing the signal.

Why: Dual effect: higher frequency means more sampling events (in MTBF denominator), but also determines resolution time per stage (T_clk - t_setup).

Find it: The clock driving your synchronizer flip-flops in the destination domain.

Metastability Window (T0)

What: Time aperture around the clock edge where data transitions cause metastability - essentially the setup + hold region.

Why: Appears in MTBF denominator. Wider window = higher probability of capturing a transition during the vulnerable period.

Find it: Device datasheet, or typical values:
• Xilinx 7-series: 40-60 ps
• Xilinx UltraScale: 30-50 ps
• Intel: 50-70 ps

Metastability Time Constant

What: Time constant of the flip-flop's regenerative feedback loop. Metastability resolves as exp(-t/τ).

Why: In MTBF exponent: each τ of resolution time improves MTBF by e (~2.7x). Smaller τ = faster resolution = exponentially better reliability.

Find it: Device datasheet. Typical values:
• Xilinx 7-series: ~20 ps
• Xilinx UltraScale: ~15 ps
• General range: 10-30 ps

Synchronizer Stages

What: Number of flip-flops in your synchronizer chain.

Why: Each stage adds ~T_clk of resolution time to the exponent. Going from 2 to 3 stages typically improves MTBF by 10^10x or more. Costs 1 cycle latency per stage.

Find it: Check your RTL. Standard is 2, use 3 for high-reliability or fast clocks.

Flip-Flop Setup Time

What: Setup time of each synchronizer flip-flop. Data must be stable this long before the capturing edge.

Why: Subtracted from each clock period when calculating resolution time: t_resolve = stages × (T_clk - t_setup). Smaller is better.

Find it: Device datasheet, timing report, or ~0.05-0.15ns for modern FPGAs.

Inter-Stage Routing Delay

What: Wire delay between synchronizer flip-flops. Subtracted from each clock period along with setup time.

Why: Reduces available resolution time: t_resolve = stages × (T_clk - t_setup - t_routing). Tight placement minimizes this.

Find it: Timing report inter-register routing.
• Typical: 0.2-0.5 ns
• Conservative: 0.3 ns
Use ASYNC_REG attribute to keep stages close.

Clock Frequency

What: Target operating frequency for the timing path. The clock period (1/frequency) sets the total time budget for register-to-register paths.

Why: Higher frequency means less time for logic. At 200 MHz you have 5 ns; at 500 MHz only 2 ns. If logic delay exceeds this budget, you have negative slack and timing violations.

How to find: Vivado: create_clock -period in XDC, or "Clock Summary" in timing reports. Quartus: create_clock in SDC, or TimeQuest "Clocks" panel.

Flip-Flop Setup Time (Tsu)

What: The minimum time data must be stable at the destination flip-flop's D input before the capturing clock edge arrives. Violating setup time causes the flip-flop to enter a metastable state or capture incorrect data.

Why: Setup time directly reduces your available logic delay budget. The tools subtract this from the clock period before calculating if your combinational path fits. A 0.05 ns setup time might seem small, but at 500 MHz (2 ns period), it consumes 2.5% of your budget.

How to find: In Vivado: look at detailed path reports - the "Destination Clock Path" section shows setup requirement. In Quartus: TimeQuest reports "tSU" in the Data Required Time breakdown. Device datasheets list typical values: Xilinx 7-Series: 0.03-0.05 ns, UltraScale+: 0.02-0.04 ns, Intel Cyclone V: 0.05-0.08 ns. The tool also adds library setup time automatically - check "Cell Delay" rows in timing reports.

Clock Uncertainty / Jitter

What: Worst-case variation in clock edge timing, combining jitter (random phase noise), skew (spatial variation across the chip), and any user-applied margin. This represents how much earlier or later the clock might arrive compared to ideal.

Why: Real clock edges are not perfectly periodic. Setup analysis uses pessimistic assumptions: the launch clock edge might be late and the capture edge early (or vice versa for hold). Clock uncertainty reduces your effective timing budget just like setup time does. High-jitter sources (recovered clocks from CDR, spread-spectrum clocks) can consume 100-200 ps of margin.

How to find: In Vivado: run report_clock_networks to see system jitter and clock buffer delays. Check the "Clock Uncertainty" section in timing reports - it shows jitter, skew, and set_clock_uncertainty constraints. In Quartus: TimeQuest's "Clock Setup" panel shows total uncertainty. Typical values: on-chip MMCM/PLL: 0.05-0.15 ns, recovered clocks: 0.15-0.3 ns. Add extra margin with set_clock_uncertainty -setup for safety.

Clock-to-Q Delay (Tcq / Tcko)

What: The propagation delay from the active clock edge at the source flip-flop to when its Q output becomes valid and stable. This is an intrinsic property of the flip-flop - after the clock triggers, it takes time for the internal latches to resolve and drive the output.

Why: Clock-to-Q delay is the very first delay in your data path. Your combinational logic timing budget only starts after the source register finishes outputting valid data. Unlike setup time (which squeezes from the end), Tcq eats into your budget from the start. At high frequencies, even 0.2 ns Tcq consumes 10% of a 2 ns period.

How to find: In Vivado: the "Source Clock Path" section of detailed timing reports shows Tcq as "FDRE (Prop_fdre_C_Q)" or similar. In Quartus: look for "tCO" in TimeQuest Data Arrival Time. Device datasheets also list typical Tcq: Xilinx 7-Series: 0.15-0.25 ns, UltraScale+: 0.10-0.18 ns, Intel Cyclone V: 0.15-0.30 ns. Note: timing tools use actual placed cells, so values vary by location and routing.

LUT Propagation Delay (Logic Level Estimate)

What: Average total delay for one logic level - the sum of LUT propagation delay (input to output) plus typical inter-LUT routing delay. This simplified model helps estimate how many cascaded logic stages will fit in your timing budget.

Why: Real timing paths consist of multiple logic levels (LUTs in series). By dividing your available logic time by the per-level delay, you can estimate maximum logic depth. Critical paths with 8+ levels often need restructuring - either pipelining (adding registers) or logic optimization (wider, shallower circuits).

How to find: Look at representative timing paths in your design after place-and-route. In Vivado: run report_timing -max_paths 100 and average the delays per logic level. Pure LUT delay is ~0.03-0.05 ns; routing adds ~0.05-0.15 ns depending on distance and congestion. Conservative estimates: Xilinx 7-Series: 0.10-0.15 ns/level, UltraScale+: 0.08-0.12 ns/level, Intel Cyclone V: 0.12-0.18 ns/level. Carry chains are much faster (~0.01 ns/bit).

Minimum Value

What: The smallest (most negative) value your fixed-point format must represent.

Why: Negative values require signed (two's complement) representation. The magnitude determines integer bits needed. Underestimating causes wrap-around or saturation artifacts.

How to find: Analyze worst-case values. FIR: 1.5-2x overshoot. IIR: 2-4x steady-state. Accumulators: sum of N max samples. Add 3-6 dB headroom (1-2 extra integer bits) for safety.

Maximum Value

What: The largest (most positive) value your fixed-point format must represent.

Why: Determines integer bits needed to prevent overflow. Exceeding the range causes wrap-around or saturation - severe distortion in signal processing.

How to find: Analyze peak gain. FIR: sum of coefficient magnitudes times max input. Accumulators: add log2(N) bits for N samples. Control: model overshoot. Add guard bits - multiply-accumulates grow by log2(N) bits.

Required Precision (LSB Step Size)

What: The smallest difference between adjacent representable values - your quantization step size and LSB weight.

Why: Determines fractional bits needed. Each additional bit halves the step size. Insufficient precision degrades SNR; for cascaded stages, errors accumulate.

How to find: From SNR: bits = (SNR_dB - 1.76) / 6.02, then precision = 2^(-bits). Typical values: Audio CD (96 dB): 0.00003. Video 8-bit: 0.004. Control: 0.001-0.0001. Sensor data: match ADC resolution.

Signed vs Unsigned Representation

What: Signed uses two's complement (MSB is sign bit). Unsigned treats all bits as magnitude, doubling the positive range but allowing only non-negative values.

Why: Most DSP (filters, audio) requires signed. Unsigned suits addresses, counters, and pixel values (0-255). Mixing signed/unsigned in multipliers requires care.

How to choose: Use signed for: AC-coupled signals, bipolar sensors, subtraction. Use unsigned for: inherently non-negative values (pixels, addresses). When in doubt, use signed. Q notation: SQm.n (signed), UQm.n (unsigned).

Input Reference Frequency

What: Clock frequency driving the PLL/MMCM input.

Why: Multiplied by M, divided by D and O to produce output. Must be within device limits (Xilinx: 10-800 MHz typical, Intel: varies).

Find it: Board schematic oscillator, or upstream clock source.

Desired Output Frequency

What: The clock frequency you need to generate.

Why: Calculator finds M/D/O combinations to produce this (or closest achievable).

Find it: Interface specs (DDR, PCIe, LVDS), IP requirements, or your design constraints.

VCO Minimum Frequency

What: Lower bound of the VCO operating range.

Why: VCO below minimum will not lock. Only configurations with f_vco >= this value are shown.

Find it: Datasheet. Typical minimums:
• Xilinx 7-series/UltraScale+: 600 MHz
• Intel Cyclone V: 600 MHz
• Intel Stratix 10: varies by PLL type

VCO Maximum Frequency

What: Upper bound of the VCO operating range.

Why: VCO above maximum will not lock. Configurations are filtered to keep f_vco <= this value. Speed-grade dependent.

Find it: Datasheet (speed-grade dependent):
• Xilinx 7-series: 1200-1600 MHz
• Xilinx UltraScale+: 1600-2400 MHz
• Intel Cyclone V: 1300 MHz
• Intel Stratix 10: 1600 MHz

Feedback Multiplier Maximum (M)

What: Maximum value for the feedback multiplier (CLKFBOUT_MULT on Xilinx).

Why: Multiplies input frequency to set VCO: f_vco = f_in x M / D. Higher M means higher VCO.

Find it: Datasheet:
• Xilinx MMCM: 2-64
• Xilinx PLL: 2-64
• Intel Cyclone V: 1-512
• Intel Arria 10: 1-160

Input Divider Maximum (D)

What: Maximum value for input clock divider (DIVCLK_DIVIDE on Xilinx).

Why: Divides input before the multiplier: PFD = f_in / D. Low PFD increases jitter; keep above 10 MHz.

Find it: Datasheet:
• Xilinx MMCM: 1-106
• Xilinx PLL: 1-56
• Intel Cyclone V: 1-512
• Intel Arria 10: 1-32

Output Divider Maximum (O)

What: Maximum value for output clock divider (CLKOUT_DIVIDE on Xilinx).

Why: Divides VCO to produce output: f_out = f_vco / O. Each output can use a different O value.

Find it: Datasheet:
• Xilinx MMCM: 1-128
• Xilinx PLL: 1-128
• Intel Cyclone V: 1-512
• Intel Arria 10: 1-512

Target Line Rate

What: The serial data rate you need on the wire - NOT your data throughput! Line rate includes encoding overhead (e.g., 8b/10b adds 25%).

Why: The GT PLL must lock to this exact frequency. This calculator finds divider settings that achieve your target rate.

How to find: Check your protocol spec. For Ethernet, line rate = data rate x encoding factor. For 10GbE: 10 Gbps x (66/64) = 10.3125 Gbps.

Common values:
- 1GbE: 1.25 Gbps (8b/10b)
- 10GbE: 10.3125 Gbps (64b/66b)
- PCIe Gen3: 8.0 GT/s (128b/130b)
- PCIe Gen4: 16.0 GT/s (128b/130b)

Reference Clock

What: The clock signal feeding your GT transceiver's PLL. This comes from an oscillator on your board, typically routed to dedicated REFCLK pins.

Why: Must be a clean, low-jitter source. The PLL multiplies this to generate your line rate. Poor refclk quality = poor link quality.

How to find: Check your board schematic for the GT REFCLK oscillator. Common values: 100 MHz (PCIe), 125 MHz (1GbE), 156.25 MHz (10GbE/25GbE).

Valid ranges:
- CPLL: 60-820 MHz (60-800 for GTX)
- QPLL: 60-820 MHz (40-670 for GTX)

DDR Generation

What: The memory technology standard (DDR3/4/5 or low-power variants).

Why it matters: Each generation has different refresh overhead, bank count, and burst length - all affecting efficiency.

How to find: Check your DIMM label (e.g., "DDR4-3200") or FPGA board datasheet.

Key differences:
- DDR4: Standard desktop/server, 16 banks, ~4.5% refresh
- DDR5: Newer, 32 banks, ~7.6% refresh
- LPDDR4/5: Mobile/embedded, per-bank refresh

Data Rate

What: Memory transfer rate in megatransfers per second. The number after "DDR4-" in the memory name.

Why: Directly determines peak bandwidth. Higher rates do not affect efficiency percentage.

How to find: Look at memory part number (e.g., DDR4-3200 = 3200 MT/s).

Common values:
- DDR4: 2133, 2400, 2666, 2933, 3200 MT/s
- DDR5: 4800, 5600, 6400, 7200, 8800 MT/s

Bus Width

What: Width of the data bus between memory controller and DRAM.

Why: Wider bus = more data per transfer = higher peak bandwidth.

Common values:
- 32-bit: Single LPDDR channel, some embedded FPGAs
- 64-bit: Standard single-channel desktop/server
- 72-bit: 64-bit + 8-bit ECC (server memory)
- 128-bit: Dual channel (2x 64-bit)

Number of Ranks

What: Independent sets of DRAM chips sharing the data bus. Multiple ranks allow overlapping operations.

Why: More ranks = better interleaving = ~2% efficiency bonus.

How to find: Single-sided DIMMs: 1 rank. Double-sided: often 2 ranks. Server DIMMs may have 4.

Burst Length

What: Number of consecutive data transfers per memory access command.

Why: Longer bursts amortize row access overhead over more data.

Typical values:
- BL4: 32 bytes (DDR4 chop mode)
- BL8: 64 bytes (DDR4 standard, matches cache line)
- BL16: 128 bytes (DDR5 standard)

Page Hit Rate (Row Buffer Hit Rate)

What: Percentage of accesses where the target row is already open.

Why: This is the BIGGEST efficiency factor. Page miss costs ~27ns extra.

How to estimate:
- 90-99%: Sequential streaming (video, STREAM benchmark)
- 75-85%: Well-optimized workloads with locality
- 50-70%: Mixed workloads, multiple access streams
- 20-40%: Random access, pointer chasing
- <20%: Pathological patterns

Read/Write Ratio

What: Percentage of accesses that are reads (vs writes).

Why: Switching between reads and writes requires turnaround time (~5-10ns).

How to estimate:
- 100%: Read-only (video decode, ML inference)
- 70-80%: Typical application workloads
- 50%: Balanced (MAXIMUM turnaround overhead)
- 30-40%: Write-heavy (ML training, logging)

Key insight: 50% R/W is the worst case (~8% bandwidth loss).

Memory Controller Quality

What: How sophisticated is your memory controller at scheduling commands?

Why: A good controller reorders commands to maximize bank parallelism. This can swing efficiency by 12%.

How to choose:
- FPGA Basic: Xilinx/Intel MIG with default settings
- FPGA Optimized: MIG with bank-aware mapping, command reordering
- Desktop: Intel/AMD consumer CPU controller
- Server: Xeon/EPYC server-grade controller