bitwiz

constraint-lint

Thu, 01 Jan 2026 00:00:00 +0000

The Problem

Your XDC file is code. Vivado doesn’t lint it.

create_clock -name clk156 -period 6.400 [get_ports clk_156]

The port is clk156. The clock attaches to nothing. Vivado warns once. It disappears into 200k lines of logs.

Your constraint file says the clock exists. Your log has one warning: no valid objects matched. WNS is meaningless because the domain you thought you constrained doesn’t exist. You find out in the lab.

What constraint-lint Does

Lint for XDC/SDC. Runs in CI. Turns constraint warnings into hard failures.

Resets: The Timing Event You Forgot

Sat, 03 Jan 2026 20:01:00 +0000

Timing Series: Part 6 of 6

Previous: CDC: Two Flip-Flops Are Not Magic

The Flop That Didn’t Reset

You’re debugging a sporadic startup failure. The system initializes correctly nine times out of ten. On the tenth, one module starts in a corrupted state while everything else works fine. The state machine begins in an illegal state. The counter starts at 7 instead of 0. The FIFO pointers are misaligned.

You add more reset logic. You connect the reset to more flip-flops. The problem gets worse.

CDC: Two Flip-Flops Are Not Magic

Fri, 02 Jan 2026 05:19:00 +0000

Timing Series: Part 5 of 6

Previous: Silicon Real Estate: Your Resource Budget

The Bug You Can’t Reproduce

You’re debugging a data corruption bug. It happens once every few hours under heavy load. Sometimes once a day. The data path looks fine. The control logic looks fine. You add ILA triggers. You wait. You catch it.

A control signal that pulses for one cycle is sometimes missed entirely. The path crosses clock domains. You have a 2-flop synchronizer.

Silicon Real Estate: Your Resource Budget

Wed, 31 Dec 2025 09:13:00 +0000

Timing Series: Part 4 of 6

Previous: Pipelining Without Breaking Your Protocol

Friday Afternoon

Friday afternoon. Timing met with 200 ps margin. I merged a teammate’s “small” feature branch-an extra output mux, some debug registers, maybe 2000 LUTs.

Monday morning: 847 failing paths. Six-hour build times. Demo on Thursday.

I hadn’t added logic. I’d crossed the congestion cliff.

Before merge: After merge:
LUT utilization: 89% LUT utilization: 93%
WNS: +0.200 ns WNS: -0.847 ns
Build time: 1.5 hours Build time: 6.2 hours
Failing paths: 0 Failing paths: 847

The utilization report said I was fine. 93% fits. But the router disagreed. Every wire fought for routing tracks. Critical paths detoured through congested regions. Placement became a puzzle with no good solutions.

Pipelining Without Breaking Your Protocol

Tue, 30 Dec 2025 05:20:00 +0000

Timing Series: Part 3 of 6

Previous: Understanding Timing Analysis

The Register That Broke Everything

You added a pipeline register to fix timing. The path closed. The simulation failed.

// Before: timing violation, functionally correct
assign data_out = transform(data_in);
assign valid_out = valid_in;

// After: timing clean, protocol broken
always_ff @(posedge clk) data_out <= transform(data_in);
assign valid_out = valid_in; // Still combinational

You pipelined data_out but not valid_out. For one cycle, valid_out asserts while data_out holds stale data. Downstream captures garbage.

If you registered data, register valid in the same always_ff:

Understanding Timing Analysis

Sun, 28 Dec 2025 05:25:00 +0000

Timing Series: Part 2 of 6

Previous: Constraints: The Contract You Forgot to Sign

The Path You Can’t Explain

You’re staring at this:

Slack (VIOLATED) : -0.247ns (required time - arrival time)
 Source: tx_reg[7]/Q
 Destination: fifo_wr_reg/D
 Path Group: clk_156
 Path Type: Setup (Max at Slow Process Corner)
 Requirement: 6.400ns
 Data Path Delay: 5.847ns (logic 1.423ns (24.3%) route 4.424ns (75.7%))
 Logic Levels: 4 (LUT6=3 CARRY4=1)
 Clock Path Skew: -0.360ns (DCD - SCD)
 Clock Uncertainty: 0.400ns

Data path is 5.847 ns. Period is 6.4 ns. You subtract and get 0.553 ns. That number is meaningless as “margin” because it ignores clock-to-source, clock-to-dest, setup, and uncertainty.

Constraints: The Contract You Forgot to Sign

Tue, 23 Dec 2025 15:04:00 +0000

Timing Series: Part 1 of 6

Previous: Your FPGA Lives a Lifetime While You Blink

Signoff Gates: Build Must Fail If…

Before reading further, know this: your build should fail if any of these checks fail.

Gate 1: Unconstrained endpoints must be zero

check_timing -verbose
report_exceptions -verbose

Fail if: Any constraint-related issue about clocks, unconstrained endpoints, or missing I/O delays. Also fail if any exception matches zero objects (silent no-op) or hits an unexpectedly large set.

Your FPGA Lives a Lifetime While You Blink

Mon, 22 Dec 2025 07:15:00 +0000

Timing Series: Part 0 of 6

The Moment Everything Breaks

You’re staring at a timing report. One line:

Slack: -0.5 ns (VIOLATED)

Half a nanosecond. The Place and Route tool just told you it’s not meeting timing as built. You asked it to get a signal from point A to point B in 6.4 nanoseconds. The shortest path it could find takes 6.9.

What does -0.5 ns actually look like?

About

Wed, 01 Jan 2025 00:00:00 +0000

About bitwiz

I’m Alexis, an FPGA engineer with 5+ years building high-performance digital systems.

Background

My work spans medical devices, big tech infrastructure, and custom silicon projects. I specialize in:

Streaming systems - High-throughput data pipelines and DMA engines
SerDes integration - Multi-gigabit serial links (PCIe, Ethernet, custom)
Verification automation - Cocotb frameworks, SVA, constrained random
Timing closure - Clock domain crossings, multicycle paths, physical optimization

Current Focus

DDR4/DDR5 memory subsystems
100G+ Ethernet implementations
Hardware/software co-verification
Open-source FPGA tooling

Philosophy

Write RTL like someone else will have to debug it at 2am. Because that someone might be you.