Pipelining Without Breaking Your Protocol

Tue, 30 Dec 2025 05:20:00 +0000

Timing Series: Part 3 of 6

Previous: Understanding Timing Analysis

The Register That Broke Everything

You added a pipeline register to fix timing. The path closed. The simulation failed.

// Before: timing violation, functionally correct
assign data_out = transform(data_in);
assign valid_out = valid_in;

// After: timing clean, protocol broken
always_ff @(posedge clk) data_out <= transform(data_in);
assign valid_out = valid_in; // Still combinational

You pipelined data_out but not valid_out. For one cycle, valid_out asserts while data_out holds stale data. Downstream captures garbage.

If you registered data, register valid in the same always_ff:

Pipelining on bitwiz

Pipelining Without Breaking Your Protocol

The Register That Broke Everything